In the rapidly developing field of portable devices, it is an important consideration to minimize power dissipation, in order to extend the time period of portability. Accordingly, various devices and methods have been developed to reduce power dissipation in portable devices.
The increasing use of DRAM (Dynamic Random Access Memory) in portable devices has highlighted the need for reducing power dissipation in the DRAM. Recently, several design methods of the DRAM have been actively investigated in order to reduce power dissipation in the refresh operation of the DRAM.
Refresh operations involve a series of operations that maintain data in semiconductor memories such as the DRAM. Generally, DRAM devices employ capacitors as the basic storage cell structures and DRAM devices determine the status of data according to whether charge is stored in a given capacitor cell. However, as time passes, charge that is stored in a capacitor becomes gradually discharged as a result of leakage current, thereby resulting in eventual data loss. To prevent this problem, data is preserved in the DRAM by periodically recharging the capacitor cells. This operation is referred to as a refresh operation.
A refresh operation is performed as follows. Data in the cells are read and amplified and then the data are restored in the original cells. One example of the refresh operation is a self-refresh. In a self-refresh operation, a refresh operation is performed without an external refresh command at a regular periodic interval while the DRAM is in a long-time waiting mode or in a low-power consumption mode. In the self-refresh operation, the refresh operation is continuously performed until an externally generated refresh end command is received.
Meanwhile, power supply devices provide the DRAM device with a direct current voltage level required to perform the DRAM operations. However, as mentioned above, the self-refresh operation is performed while operating in a mode when data input/output operations are not performed (e.g., in a long-time waiting mode or in a low-power mode), and therefore offers the advantage of relatively low power consumption as compared to normal operating mode. Therefore, the DRAM power supply device provides relatively weaker power levels during the refresh mode as compared to normal mode. In this manner, power consumption by the DRAM is reduced.
FIG. 1 illustrates the input and output signals for a self-refresh operation in a general power supply device used in conventional semiconductor memory. FIG. 2 is a waveform diagram of signals of the conventional power supply device shown in FIG. 1.
Referring to FIGS. 1 and 2, a conventional power supply device 100 continuously provides relatively weak power levels to a DRAM during a self-refresh operation section (an SR section A) as compared to a normal operation section in response to a self-refresh clock signal Pself input from an external source and a predetermined reference voltage Vref. At this time, the power supply device 100 may be embodied to include a differential amplifier (not shown). This is understood by those skilled in the art, and description thereof is thus omitted.
In another approach, as shown the waveform diagram of FIG. 2, the DRAM self-refresh operation may be subdivided into an active-precharge mode B and an idle mode C during the SR section A. In the active-precharge mode B, an actual refresh operation is performed. For this reason, the active-precharge mode B requires relatively strong power as compared to the idle mode C being a waiting state. However, the power that is supplied to the power supply device 100 controlled by the self-refresh clock signal Pself during the SR section A is relatively weak as compared to the normal operation section. As a result, the possibility exists that the power provided for the active-precharge mode of the self-refresh operation is insufficient. In addition, unnecessary power is consumed during the idle mode C.